Partitioning and mapping algorithms into fixed size systolic arraysMOLDOVAN, D. I; FORTES, J. A. B.IEEE transactions on computers. 1986, Vol 35, Num 1, pp 1-12, issn 0018-9340Article

Detailed modeling and reliability analysis of fault-tolerant processor arraysLOPEZ-BENITEZ, N; FORTES, J. A. B.IEEE transactions on computers. 1992, Vol 41, Num 9, pp 1193-1200, issn 0018-9340Article

Independent partitioning of algorithms with uniform depenciesWEIJIA SHANG; FORTES, J. A. B.IEEE transactions on computers. 1992, Vol 41, Num 2, pp 190-206, issn 0018-9340Article

On time mapping of uniform dependence algorithms into lower dimensional processor arraysWEIJIA SHANG; FORTES, J. A. B.IEEE transactions on parallel and distributed systems. 1992, Vol 3, Num 3, pp 350-363Article

A fast VLSI-efficient self-routing permutation networkCAM, H; FORTES, J. A. B.IEEE transactions on computers. 1995, Vol 44, Num 3, pp 448-452, issn 0018-9340Article

Frames: a simple characterization of permutations realized by frequently used networksCAM, H; FORTES, J. A. B.IEEE transactions on computers. 1995, Vol 44, Num 5, pp 695-697, issn 0018-9340Article

Communication-minimal partitioning and data alignment for affine nested loopsLEE, H.-J; FORTES, J. A. B.Computer journal (Print). 1997, Vol 40, Num 6, pp 302-310, issn 0010-4620Article

On the design of inphase an quadrature filters for delay compensationBEN-MILED, Z; TIEMANN, J. J; HELBIG, W. A et al.IEEE transactions on signal processing. 1994, Vol 42, Num 9, pp 2501-2503, issn 1053-587XArticle

Modular mappings and data distribution independent computationsLEE, H.-J; FORTES, J. A. B.Parallel processing letters. 1997, Vol 7, Num 2, pp 169-180, issn 0129-6264Conference Paper